The synchronous transmission protocols: SDLC (Synchronous Data Link Control) or HDLC (High Level Data Link Control) are bit based protocols which define the structures and rules which govern the synchronous data transmissions.
These protocols are well known and extensively described in the literature.
According to these protocols, the bit stream comprises frames built according to the following fixed scheme:
The frame starts with a flag which has the following pattern 01111110, i.e. it comprises a number f of consecutive bits at a first value, i.e. 6 bits at 1. Then an information block follows, which comprises a variable number of characters including, address, control and data (if any) characters. In this block, a bit at the second value, i.e. 0 is inserted after (f-1) consecutive bits at the first value i.e. after 5 bits at 1, according to the present implementations, to prevent the flag pattern from happening in the information block. In some cases, the frames comprise specific significance patterns such as idle or abort patterns which comprise more than f consecutive bits at the first value, no zeroes are inserted in these patterns.
After the information block, frame check sequence characters are appended (with inserted zeroes) to provide an error detection facility. The frame is ended by a flag which may be used as the starting flag of the next frame.
The Communications controllers or front end processors such as the IBM 3725 or 3745 Communication controllers are attached to HDLC lines through line scanning means. Conventional implementations of the line scanning function of HDLC lines, such as described in U.S. Pat. No. 4,493,051 has taken benefit of this specificity in offering a bit by bit processing of the HDLC bit streams. In the scanning means, which control the scanning of a plurality of lines, a memory area is assigned to each line and comprises a control block to store the information relative to the line. Each processed bit (either a received bit or a bit to be transmitted) is managed separately, which leads to an updating of the control block information for:
zero insertion deletion PA1 flag, abort, idle configurations recognition. generation PA1 frame check sequence accumulation verification
The very high speed transmissions require an efficient implementation of the scanning function, which cannot be reached with the conventional bit by bit processing, the performance of which is limited by the time spent to read and write the control block information. Two memory accesses are needed at each processed bit, since the control block has to be read, updated as a function of the processed bit and the updated information has to be re-written into the control block.
Also, there is another performance limitation due to the path delay of the combinatorial update process of the control blocks.